This invention relates to providing an improved silicon interposer system. More particularly, this invention relates to methods and apparatus arrangements providing a means for implementing a universal silicon interposer enabling the selective use of multiple proprietary microelectronic devices without requiring a redesign of the end-use substrate format.
Implementation of three dimensional (3D) chip stacking using, among other techniques, Through Silicon Vias (TSVs) has allowed microelectronics manufacturers to increase device bandwidth, reduce power consumption, and shrink the physical form factor of the resultant microelectronic devices. Briefly stated, a TSV connection is a galvanic connection between the two sides of a silicon wafer, which is electrically isolated from the substrate and from other TSV connections.
One problem encountered within emerging microelectronic technologies is the initial lack of device format standards. For example, two independent manufacturers may produce equivalent 3D-IC devices having differing (non-compatible) TSV contact pin patterns, thus requiring the end-use application to adopt a manufacturer-specific connection format. A means for enabling the selective use of multiple proprietary microelectronic devices, without the need to substantially alter the end-use application, would benefit the industry and ultimately consumers through lower product development costs, lower production costs, and reduced production risks associated with dependence on single-source suppliers.